1. Field of the Invention
The present invention relates to a semiconductor memory integrated circuit formed through integration of memory cells that includes access transistors and memory capacitors mounted on a semiconductor substrate.
2. Description of the Related Art
In a semiconductor memory integrated circuit typified by Dynamic Random Access Memory (DRAM), an increase in packing density can be realized through reduction of the area on the primary surface of a semiconductor substrate occupied by a memory capacitor, thereby enabling implementation of large-scale integration. In this connection, there have already been devised a technique of forming a stacked memory capacitor formed on the primary surface of the semiconductor substrate so as to extend upward and a technique of forming a trench memory capacitor by etching a trench on the primary surface of the semiconductor substrate. An example of DRAM having such a memory capacitor is one in which a single transistor memory cell comprising one access transistor and one memory capacitor is used as a basic unit of memory. In this type of DRAM, a unit memory cell is formed from a comparatively small number of functional circuit elements, and thus occupies a smaller area. Therefore, the number of memory cells per unit area in the memory element integrated device, i.e., the packaging density of memory element integrated device, can be sufficiently increased. However, in recent years, supply voltage has tended to become lower with the progress in microprocessing technology. This tendency is accompanied by a reduction in a signal amplitude; thus, reliably reading an information signal from the memory cell has become more difficult.
In typical DRAM, one of a pair of bit lines transmits an information signal from a memory cell at a read address, and the remaining bit line receives a signal from a dummy cell. A gate-operational flip-flop circuit (a gated flip-flop) is used as a sense circuit to measure a potential difference between the two bit lines, thereby detecting information. When the foregoing single-transistor-memory-cell DRAM performs a sensing operation such as that set forth, a voltage corresponding to an error in signal potential settings of the dummy cell and to variations in supply potential cannot be utilized as a dead zone of the supply potential. For this reason, a decrease in supply potential associated with progress in microprocessing technique renders stable storing operations difficult. Further, DRAM required for operating at high speed encounters a problem of unstable operations caused by noise developing in the integrated circuit.
To prevent these problems, a two-transistor-memory-cell DRAM has been proposed as described in, e.g., U.S. Pat. No. 5,329,479 and Japanese Patent Application Laid-open No. 61-240497 and 62-65295. In this two-transistor-memory-cell DRAM, a single memory cell is formed from two transistors and one capacitor. An identical information signal is complementarily transmitted from the memory cell to each of a pair of bit lines. In this integrated circuit, a complementary information signal representing identical information is supplied to each of the pair of bit lines, thereby preventing formation of a dead zone in a sense circuit which is connected to a portion of the bit line pair and which amplifies the information signal. As a result, even in a case where the integrated circuit operates at a low voltage and at high speed, stable storing operations can be ensured.
In the two-transistor-memory-cell semiconductor memory integrated circuit comprising two access transistors and one memory capacitor, since the area occupied by the memory cell becomes greater than that in the case of the single-transistor-memory-cell DRAM, integration of DRAM inevitably involves deterioration of packing density. Particularly, in a case where the pitch--at which bit line pairs extending in a certain direction are arranged--is reduced in order to finely process the memory cell, sense circuits for the purpose of detecting an information signal from the bit lines must also be arranged at smaller pitches. However, arrangement of sense circuits at smaller pitches is not easy.